With the number of conductive wiring layers in the integrated circuit (IC) increases, metal layer structure consisting of two or more layers has gradually become a design adopted in many ICs. The metal layers usually are separated by inter-metal dielectrics (IMD). The metal conductive lines on the upper metal layer and the lower metal layer are connected by via holes. The conventional approach to interconnect in the metal is to deposit a dielectric layer on a substrate already having metal conductive lines formed thereon; next, form a vertical via opening in the dielectric layer through a selected via opening pattern; then form a conductive layer on the substrate that is made from material same as or different from the metal conductive lines; finally flatten the conductive layer and define the interconnection in the metal layers.
As the semiconductor elements are continuously miniaturized and the line width shrinks constantly, the distance between the metal lines also reduces constantly. As a result, the phenomenon of parasitic capacitor becomes more severe. The value of the dielectric constant of the IMD material becomes very important. The greater the dielectric constant of the IMD material, the more likely the parasitic capacitor occurs. The RC delay is even more serious, and circuit transmission speed decreases. By reducing the dielectric constant of the dielectric layer, the RC delay becomes lower and operation speed of elements may increase.
In the past, silicon dioxide film is being used as the dielectric material between the conductive lines. It has dielectric constant 3.9. In practice, the silicon dioxide film formed by chemical vapor deposition (CVD) has dielectric constant of 4.2, which is greater than the silicon dioxide film formed by thermal oxidization. For elements in the field of nanotechnology, the dielectric constant of such a silicon dioxide film cannot be further reduced. The resulting parasite capacitor effect affects signal transmission delay in the multi-layer conductive lines and signal cross talk incurred among them.
At present Spin-on-glass (SOG) is widely used in the semiconductor industry. It can form a lower dielectric constant, improved thermal stability, lower leakage current and has a simpler fabrication process. Thus it is a desired material for flattening or ditch filling in the semiconductor manufacturing process.
However, the SOG material and the dielectric layer of a lower dielectric constant now being used tend to form metal plug and result in poison in the downstream fabrication processes due to the dielectric layer of a lower dielectric constant mostly is porous and water absorbing and often contains moisture.